Backend memory with air gaps in upper metal layers

ABSTRACT

An example IC device includes a frontend layer and a backend layer with a metallization stack. The metallization stack includes a backend memory layer with a plurality of memory cells with backend transistors, and a layer with a plurality of conductive interconnects (e.g., a plurality of conductive lines) and air gaps between adjacent ones of the plurality of interconnects. Providing air gaps in upper metal layers of metallization stacks of IC devices may advantageously reduce parasitic effects in the IC devices because such effects are typically proportional to the dielectric constant of a surrounding medium. In turn, reduction in the parasitic effects may lead to improvements in performance of, or requirements placed on, the backend memory.

BACKGROUND

Embedded memory is important to the performance of modern system-on-a-chip (SoC) technology. Low power and high density embedded memory is used in many different computer products and further improvements are always desirable.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

FIG. 1 provides an electric circuit diagram of a one access transistor (1T) and one capacitor (1C) (1T-1C) memory cell, according to some embodiments of the present disclosure.

FIGS. 2A-2B are cross-sectional and plan views, respectively, of an example thin-film transistor (TFT) based memory cell with an access TFT, according to some embodiments of the present disclosure.

FIGS. 3A-3B are cross-sectional views of an example structure of the access TFT in the memory cell of FIGS. 2A-2B, according to some embodiments of the present disclosure.

FIG. 4 provides a schematic illustration of an integrated circuit (IC) device with backend memory and air gaps in upper metal layers, according to some embodiments of the present disclosure.

FIG. 5 provides a cross-sectional side view of an example IC device with backend memory and air gaps in upper metal layers, according to some embodiments of the present disclosure.

FIGS. 6A-6D provide cross-sectional side views at different stages of fabricating an IC device with backend memory and air gaps in upper metal layers, according to some embodiments of the present disclosure.

FIGS. 7A-7B are top views of a wafer and dies that include IC devices with backend memory and air gaps in upper metal layers in accordance with any of the embodiments disclosed herein.

FIG. 8 is a cross-sectional side view of one side of an IC device that may implement backend memory and air gaps in upper metal layers in accordance with any of the embodiments disclosed herein.

FIG. 9 is a cross-sectional side view of an IC package that may include one or more IC devices with backend memory and air gaps in upper metal layers in accordance with any of the embodiments disclosed herein.

FIG. 10 is a cross-sectional side view of an IC device assembly that may include one or more IC devices with backend memory and air gaps in upper metal layers in accordance with any of the embodiments disclosed herein.

FIG. 11 is a block diagram of an example computing device that may include one or more IC devices with backend memory and air gaps in upper metal layers in accordance with any of the embodiments disclosed herein.

DETAILED DESCRIPTION

Overview

The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.

IC devices with backend memory and air gaps in upper metal layers, as well as associated systems and methods, are disclosed. An example IC device includes a frontend layer with a plurality of frontend transistors (e.g., logic transistors) and a backend layer with a metallization stack that includes a backend memory layer with a plurality of memory cells with backend transistors, and a layer with a plurality of conductive interconnects (e.g., a plurality of conductive lines) and air gaps between adjacent ones of the plurality of interconnects. Interchangeably, the frontend layer may also be referred to as a front end of line (FEOL) layer, while the backend layer may also be referred to as a back end of line (BEOL) layer, or a plurality of BEOL layers. The backend memory layer may be between the frontend layer and the layer with the air gaps, with no other backend memory included above the layer with the air gaps, which means that the air gaps may be provided in upper metal layers of the metallization stack. Providing air gaps in upper metal layers of metallization stacks of IC devices may advantageously reduce parasitic effects (e.g., parasitic capacitance) in the IC devices because such effects are typically proportional to the dielectric constant of a surrounding medium. Since the dielectric constant of air is equal to about 1 and is lower than that of any solid dielectric material typically included between interconnects of a metallization stack, replacing at least some of the solid dielectric material with air gaps effectively reduces the average dielectric constant of the surrounding medium around the interconnects, thus reducing the parasitic effects. In turn, reduction in the parasitic effects may lead to improvements in performance of, or requirements placed on, the backend memory. For example, introducing air gaps in the upper metal layers of an IC device may lead to a reduction of bit-line delay of backend memory included in lower metal layers of the IC device.

In the following, some descriptions may refer to backend memory being TFT-based memory. However, embodiments of the present disclosure are equally applicable to backend memory implemented using layer transfer instead of, or in addition to, TFTs. Furthermore, some descriptions may refer to a particular source or drain (S/D) region or contact of a transistor being either a source region/contact or a drain region/contact. However, unless specified otherwise, which region/contact of a transistor is considered to be a source region/contact and which region/contact is considered to be a drain region/contact is not important because, as is common in the field of field-effect transistors (FETs), designations of source and drain are often interchangeable. Therefore, descriptions of some illustrative embodiments of the source and drain regions/contacts provided herein are applicable to embodiments where the designation of source and drain regions/contacts may be reversed. For example, while some descriptions provided herein may refer to transistors being bottom-gated transistors, embodiments of the present disclosure are not limited to only this design and include transistors of various other architectures, or a mixture of different architectures. For example, in various embodiments, transistors described herein, may include bottom-gated transistors, top-gated transistors, FinFETs, nanowire transistors, nanoribbon transistors, planar transistors, etc., all of which being within the scope of the present disclosure. Furthermore, although descriptions of the present disclosure may refer to logic devices or memory cells provided in a given layer of an IC device, each layer of the IC devices described herein may also include other types of devices besides logic or memory devices described herein. For example, in some embodiments, FEOL layers with logic transistors may also include memory cells and/or BEOL layers with memory cells may also include logic transistors.

In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, a term “interconnect” may be used to describe any element formed of an electrically conductive material for providing electrical connectivity to one or more components associated with an IC or/and between various such components. In general, the term “interconnect” may refer to both conductive lines (or, simply, “lines,” also sometimes referred to as “traces” or “trenches”) and conductive vias (or, simply, “vias”). In general, in context of interconnects, the term “conductive line” may be used to describe an electrically conductive element isolated by an insulator material (e.g., a low-k dielectric material) that is provided within the plane of an IC die. Such lines are typically stacked into several levels, or several layers, of a metallization stack. On the other hand, the term “via” may be used to describe an electrically conductive element that interconnects two or more lines of different levels. To that end, a via may be provided substantially perpendicularly to the plane of an IC die and may interconnect two lines in adjacent levels or two lines in not adjacent levels. A term “metallization stack” may be used to refer to a stack of one or more interconnects for providing connectivity to different circuit components of an IC chip. Sometimes, lines and vias may be referred to as “metal traces” and “metal vias”, respectively, to highlight the fact that these elements include electrically conductive materials such as metals.

In another example, the terms “package” and “IC package” are synonymous, as are the terms “die” and “IC die,” the term “insulating” means “electrically insulating,” the term “conducting” means “electrically conducting,” unless otherwise specified. Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, “an electrically conductive material” may include one or more electrically conductive materials. If used, the terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc., the term “high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide, while the term “low-k dielectric” refers to a material having a lower dielectric constant than silicon oxide. Furthermore, the term “connected” may be used to describe a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” may be used to describe either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” may be used to describe one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20% of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−5-20% of a target value based on the context of a particular value as described herein or as known in the art.

For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation “A/B/C” means (A), (B), and/or (C).

The description may use the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, if a collection of drawings designated with different letters are present, e.g., FIGS. 2A-2B, such a collection may be referred to herein without the letters, e.g., as “FIG. 2 .”

In the drawings, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, but it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication.

Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

Various IC devices with backend memory and air gaps in upper metal layers as described herein may be implemented in, or associated with, one or more components associated with an IC or/and may be implemented between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.

Example Backend Memory

For purposes of illustrating IC devices with backend memory and air gaps in upper metal layers as described herein, it might be useful to first understand phenomena that may come into play in certain IC arrangements. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.

Some memory devices may be considered “standalone” devices in that they are included in a chip that does not also include compute logic (where, as used herein, the term “compute logic devices” or simply “compute logic” or “logic devices,” refers to IC components, e.g., transistors, for performing computing/processing operations). Other memory devices may be included in a chip along with compute logic and may be referred to as “embedded” memory devices. Using embedded memory to support compute logic may improve performance by bringing the memory and the compute logic closer together and eliminating interfaces that increase latency. Various embodiments of the present disclosure relate to embedded memory arrays, as well as corresponding methods and devices.

Some embodiments of the present disclosure may refer to dynamic random-access memory (DRAM) and in particular, embedded DRAM (eDRAM), because this type of memory has been introduced in the past to address the limitation in density and standby power of other types or memory. However, embodiments of the present disclosure are equally applicable to backed memory implemented using other technologies. Thus, in general, backend memory described herein may be implemented as eDRAM cells, spin-transfer torque random-access memory (STTRAM) cells, resistive random-access memory (RRAM) cells, or any other nonvolatile memory cells.

As an example, a DRAM cell may include a capacitor for storing a bit value, or a memory state (e.g., logical “1” or “0”) of the cell, and an access transistor controlling access to the cell (e.g., access to write information to the cell or access to read information from the cell). Such a memory cell may be referred to as a “1T-1C memory cell,” highlighting the fact that it uses one transistor (i.e., “1T” in the term “1T-1C memory cell”) and one capacitor (i.e., “1C” in the term “1T-1C memory cell”). The capacitor of a 1T-1C memory cell may be coupled to one S/D terminal/region of the access transistor (e.g., to the source terminal/region of the access transistor), while the other S/D terminal/region of the access transistor (e.g., to the drain terminal/region) may be coupled to a bit-line (BL), and a gate terminal of the access transistor may be coupled to a word-line (WL). Since such a memory cell can be fabricated with as little as a single access transistor, it can provide higher density and lower standby power versus some other types of memory in the same process technology.

Various 1T-1C memory cells have, conventionally, been implemented with access transistors being FEOL, logic-process based, transistors implemented in an upper-most layer of a semiconductor substrate. However, using standard logic transistors as access transistors of 1T-1C memory cells creates several challenges.

One challenge relates to the leakage of an access transistor, i.e., current flowing between the source and the drain of a transistor when the transistor is in an “off” state. Since reducing leakage of logic transistors in the scaled technology is difficult, implementing 1T-1C memory in advanced technology nodes (e.g., 10 nanometer (nm), 7 nm, 5 nm, and beyond) can be challenging. In particular, given a certain access transistor leakage, capacitance of the capacitor of a 1T-1C memory cell should be large enough so that sufficient charge can be stored on the capacitor to meet the corresponding refresh times. However, continuous desire to decrease size of electronic components dictates that the macro area of memory arrays continues to decrease, placing limitations on how large the top area (i.e., the footprint) of a given capacitor is allowed to be, which means that capacitors need to be taller in order to have both sufficiently small footprint area and sufficiently large capacitance. As the capacitor dimensions continue to scale, this in turn creates a challenge for etching the openings for forming the capacitors as tall capacitors with small footprint areas require higher aspect ratio openings, something which is not easy to achieve.

Another challenge associated with the use of logic transistors in 1T-1C memory cells relates to the location of the capacitors such memory cells. Namely, it may be desirable to provide capacitors in metal layers close to their corresponding access transistors. Since logic transistors are implemented as FEOL transistors provided directly on the semiconductor substrate, the corresponding capacitors of 1T-1C memory cells then have to be embedded in lower metal layers in order to be close enough to the logic access transistors. As the pitches of lower metal layers aggressively scale in advanced technology nodes, embedding the capacitors in the lower metal layers poses significant challenges to the scaling of 1T-1C based memory.

Yet another challenge resides in that, given a usable surface area of a substrate, there are only so many FEOL transistors that can be formed in that area, placing a significant limitation on the density of memory cells of a memory array.

Implementing memory in the backend of an IC device, i.e., in one or more BEOL layers may address some of the challenges described above.

Backend memory may be implemented using TFTs as access transistors of the memory cells embedded in the BEOL layers. A TFT is a special kind of a field-effect transistor made by depositing a thin film of an active semiconductor material, as well as a dielectric layer and metallic contacts, over a supporting layer that may be a non-conducting layer and a non-semiconductor layer. At least a portion of the active semiconductor material forms a channel of the TFT. This is different from conventional, non-TFT, FEOL logic transistors where the active semiconductor channel material is typically a part of a semiconductor substrate, e.g., a part of a silicon wafer. Using TFTs as access transistors of memory cells provides several advantages and enables unique architectures that were not possible with conventional, FEOL logic transistors. For example, one advantage is that a TFT may have substantially lower leakage than a logic transistor, allowing to relax the demands on the large capacitance placed on a capacitor of a 1T-1C memory cell. In other words, using a lower leakage TFT in a 1T-1C memory cell allows the memory cell to use a capacitor with lower capacitance and smaller aspect ratio while still meeting the same data retention requirements of other approaches, alleviating the scaling challenges of capacitors.

Additionally, or alternatively, to TFT-based memory, backend memory may be implemented using layer transfer to form access transistors of the memory cells embedded in the BEOL layer. Layer transfer may include epitaxially growing a layer of a highly crystalline semiconductor material on another substrate and then transferring the layer, or a portion thereof, to embed it in the BEOL layer provided over a second substrate. Channel regions of backend transistors then include at least portions of such transferred semiconductor material layer. Performing layer transfer may advantageously allow forming non-planar transistors, such as FinFETs, nanowire transistors, or nanoribbon transistors, in the BEOL layer. In some embodiments, transistors, or portions thereof (e.g., S/D regions) may be formed on the first substrate (i.e., on the substrate on which a layer of a highly crystalline semiconductor material is grown) before the layer transfer takes place, and then a layer with such transistors, or portions thereof, is transferred.

Layer transfer approach for providing backend memory may be particularly suitable for forming access transistors with channel regions formed of substantially single-crystalline semiconductor materials. On the other hand, TFT-based backend memory may be seen as an example of a monolithic integration approach because the semiconductor materials for the channel regions are deposited in a BEOL layer of an IC device, as opposed to being epitaxially grown elsewhere and then transferred, which may be particularly suitable for forming access transistors with channels formed of polycrystalline, polymorphous, or amorphous semiconductor materials, or various other thin-film channel materials. Whether a semiconductor material of a channel region for a given backend device (e.g., a backend transistor) has been provided by monolithic integration approach or by layer transfer can be identified by inspecting grain size of active semiconductor material of the device (e.g., of the semiconductor material of the channel region of a backend transistor). An average grain size of the semiconductor material being between about 0.5 and 1 millimeters (in which case the material may be polycrystalline) or smaller than about 0.5 millimeter (in which case the material may be polymorphous) may be indicative of the semiconductor material having been deposited in the BEOL layer of the device (i.e., monolithic integration approach), e.g., to form a TFT. On the other hand, an average grain size of the semiconductor material being equal to or greater than about 1 millimeter (in which case the material may be a single-crystal material) may be indicative of the semiconductor material having been included in the BEOL layer of the device by layer transfer. The discussions of monolithic integration vs. layer transfer approaches for forming backend memory are equally applicable to backend transistors that are not part of a memory array (e.g., if backend transistors are implemented in an IC device to serve as logic transistors, switches, or for any other purposes or in any other circuits).

Moving access transistors to the BEOL layers of an advanced complementary metal oxide semiconductor (CMOS) process, either by monolithic integration (e.g., using TFTs) or by layer transfer, means that their corresponding capacitors can be implemented in the upper metal layers with correspondingly thicker interlayer dielectric (ILD) layer and larger metal pitch to achieve higher capacitance. This eases the integration challenge introduced by embedding the capacitors. Furthermore, when at least some access transistors are implemented as backend transistors, at least portions of different memory cells may be provided in different BEOL layers above a substrate, thus enabling a stacked architecture of memory arrays. In this context, the term “above” refers to the BEOL layer being further away from the FEOL layer of an IC device (e.g., the IC device 500 shown in FIG. 5 ).

FIG. 1 provides an electric circuit diagram of an 1T-1C memory cell 100, according to some embodiments of the present disclosure. As shown, the 1T-1C cell 100 may include an access transistor 110 and a capacitor 120. The access transistor 110 has a gate terminal, a source terminal, and a drain terminal, indicated in the example of FIG. 1 as terminals G, S, and D, respectively. In the following, the terms “terminal” and “electrode” may be used interchangeably. Furthermore, for S/D terminals, the terms “terminal” and “region” may be used interchangeably.

As shown in FIG. 1 , in the 1T-1C cell 100, the gate terminal of the access transistor 110 may be coupled to a WL 150, one of the S/D terminals of the access transistor 110 may be coupled to a BL 140, and the other one of the S/D terminals of the access transistor 110 may be coupled to a first electrode of the capacitor 120. As also shown in FIG. 1 , the other electrode of the capacitor 120 may be coupled to a capacitor plate-line (PL) 160 (also sometimes referred to as a “select-line” (SL)). As is known in the art, WL, BL, and PL may be used together to read and program the capacitor 120.

Each of the BL 140, the WL 150, and the PL 160, as well as intermediate elements coupling these lines to various terminals described herein, may be formed of any suitable electrically conductive material, which may include an alloy or a stack of multiple electrically conductive materials. In some embodiments, such electrically conductive materials may include one or more metals or metal alloys, with metals such as ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum. In some embodiments, such electrically conductive materials may include one or more electrically conductive alloys oxides or carbides of one or more metals.

In some embodiments, the access transistor 110 may be a TFT. In other embodiments, the access transistor 110 may be not a TFT, e.g., a transistor formed on a crystalline semiconductor material provided in the backend of an IC device using layer transfer. For example, in some such embodiments, the access transistor 110 may be a FinFET, a nanowire, or a nanoribbon transistor.

FIGS. 2A-2B are cross-sectional (y-z plane) and plan (y-x plane) views, respectively, of an example access TFT 210 of a given TFT-based memory cell 200, according to some embodiments of the present disclosure. For example, the access TFT 210 may be the access transistor 110 of FIG. 1 , and the memory cell 200 may be the memory cell 100 of FIG. 1 . FIGS. 3A-3B are cross-sectional views (x-z and y-z planes) of an example structure of the access TFT 210 in the TFT-based memory cell 200 of FIGS. 2A-2B, according to some embodiments of the present disclosure. The memory cell 200 shown in FIGS. 2 and 3 is an example of a memory cell that may be implemented to realize one or more of the memory cells of the backend memory of IC devices with backend memory and air gaps in upper metal layers as described herein, e.g., of IC devices 400 or 500 as described herein. In some embodiments of the IC devices 400 or 500 as described herein, multiple memory cells 200 may be arranged in a stacked architecture, i.e., when different memory cells such as the one shown in FIGS. 2 and 3 are stacked in different BEOL layers.

As shown in FIG. 2 , the TFT-based memory cell 200 may include a WL 250 (which may be an example of the WL 150 of FIG. 1 ) to supply a gate signal. As also shown in FIG. 2 , the TFT-based memory cell 200 may further include an access TFT 210 that includes a channel layer and is configured to control transfer of a memory state of the memory cell between a first region and a second region of the channel layer in response to the gate signal (channel layer and first and second regions described in greater detail below, e.g., with reference to FIG. 3 ). In some embodiments, the access TFT 210 may be provided above the WL 250 coupled to the memory cell 200. As also shown in FIG. 2 , the memory cell 200 may further include a BL 240 to transfer the memory state and coupled to the first region of the channel layer of the access TFT 210, and a storage node 230 coupled to the second region of the channel layer of the access TFT 210. Although not specifically shown in FIG. 2 , the memory cell 200 further includes a capacitor such as the capacitor 120 of FIG. 1 , e.g., a metal-insulator-metal (MIM) capacitor coupled to the storage node 230 and configured to store the memory state of the memory cell 200.

Turning to the details of FIG. 2 , the access TFT 210 in the memory cell 200 may be coupled to or controlled by WL 250, which, in some embodiments, may serve as the gate of the access TFT 210. A BL 240 (which may be an example of the BL 140 of FIG. 1 ) may be coupled to one of the S/D regions (or to one of the S/D contacts or terminals) of the access TFT 210 and a storage node 230 may be coupled to the other one of the S/D regions of the access TFT 210. In some embodiments, the BL 240 may serve as a first S/D contact and the storage node 230 may serve as the second S/D contact of the access TFT 210. The BL 240 may be connected to a sense amplifier and a BL driver which may, e.g., be provided in a memory peripheral circuit associated with a memory array that includes the memory cell 200. In some embodiments, for a given memory cell 200, the WL 250 may be formed in a metal layer Mx (where x is an integer indicating a specific layer) of the BEOL of an IC device, while the access TFT 210, the storage node 230, and the BL 240 may be formed in a metal layer Mx+1 of the BEOL of an IC device, i.e., the metal layer above the metal layer Mx, e.g., directly above the metal layer Mx (as illustrated in FIGS. 2 and 3 ). A capacitor of the memory cell 200 may then be formed in a metal layer Mx+2 of the BEOL of an IC device, e.g., directly above the metal layer Mx+1.

FIGS. 3A-3B illustrate further details of the access TFT 210. As shown in FIGS. 3A-3B, in some embodiments, the access TFT 210 may be provided substantially above the WL 250. In some embodiments, the access TFT 210 may be a bottom-gated TFT in that its gate stack comprising a gate dielectric 216 and a gate electrode 214 may be provided below its channel layer (also referred to as “active layer”) 218, e.g., between the channel layer 218 and the WL 250, and the channel layer 218 may be between the gate stack and the BL 240 forming one of the S/D terminals, e.g., the drain terminal, of the access TFT 210 and the storage node 230 forming another one of the S/D terminals, e.g., the source terminal, of the access TFT 210 (again, in other embodiments, this example designation of S/D terminals may be reversed). Thus, the WL 250 may be between an FEOL layer 420 as shown in FIG. 4 and the gate electrode 214, and the BL 240 may be further away from the FEOL layer 420 than the channel layer 218.

The channel layer 218 may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, the channel layer 218 may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In general, the channel layer 218 may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N- or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphite, and black phosphorus, each of which may possibly be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. In particular, the channel layer 218 may be formed of a thin-film material. Some such materials may be deposited at relatively low temperatures, which allows depositing them within the thermal budgets imposed on back end fabrication to avoid damaging the front end components such as the logic devices of the FEOL layer of an IC device 400 or 500. In some embodiments, the channel layer 218 may have a thickness between about 5 and 75 nanometers, including all values and ranges therein.

The S/D electrodes of the access TFT 210, shown in various figures as provided by the corresponding BL 240 and the source node 240, respectively, may include any suitable electrically conductive material, alloy, or a stack of multiple electrically conductive materials. In some embodiments, the S/D electrodes of the access TFT 210 may include one or more metals or metal alloys, with metals e.g., copper, ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum, tantalum nitride, tungsten, doped silicon, doped germanium, or alloys and mixtures of these. In some embodiments, the S/D electrodes of the access TFT 210 may include one or more electrically conductive alloys, oxides, or carbides of one or more metals. In some embodiments, the S/D electrodes of the access TFT 210 may include a doped semiconductor, such as silicon or another semiconductor doped with an N-type dopant or a P-type dopant. Metals may provide higher conductivity, while doped semiconductors may be easier to pattern during fabrication. In some embodiments, the S/D electrodes of the access TFT 210 may have a thickness (i.e., dimension measured along the z-axis of the example coordinate system shown in the present drawings) between about 2 nanometers and 1000 nanometers, preferably between about 2 nanometers and 100 nanometers.

A gate dielectric 216 may laterally surround the channel layer 218, and the gate electrode 214 may laterally surround the gate dielectric 216 such that the gate dielectric 216 is disposed between the gate electrode 214 and the channel layer 218. In various embodiments, the gate dielectric 216 may include one or more high-k dielectric materials and may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric 216 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric 216 during manufacture of the access TFT 210 to improve the quality of the gate dielectric 216. In some embodiments, the gate dielectric 216 may have a thickness between about 0.5 nanometers and 3 nanometers, including all values and ranges therein, e.g., between about 1 and 3 nanometers, or between about 1 and 2 nanometers.

In some embodiments, the gate dielectric 216 may be a multilayer gate dielectric, e.g., it may include any of the high-k dielectric materials in one layer and a layer of IGZO. In some embodiments, the gate stack (i.e., a combination of the gate dielectric 216 and the gate electrode 214) may be arranged so that the IGZO is disposed between the high-k dielectric and the channel layer 218. In such embodiments, the IGZO may be in contact with the channel layer 218 and may provide the interface between the channel layer 218 and the remainder of the multilayer gate dielectric 216. The IGZO may have a gallium to indium ratio of 1:1, a gallium to indium ratio greater than 1 (e.g., 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1), and/or a gallium to indium ratio less than 1 (e.g., 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10).

The gate electrode 214 may include at least one P-type work function metal or N-type work function metal, depending on whether the access TFT 210 is a P-type metal oxide semiconductor (PMOS) transistor or an N-type metal oxide semiconductor (NMOS) transistor. For a PMOS transistor, metals that may be used for the gate electrode 214 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, metals that may be used for the gate electrode 214 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode 214 may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as to act as a diffusion barrier layer, described below.

FIGS. 3A-3B further illustrate that the bottom-gated access TFT 210 may further, optionally, include layers such as a diffusion barrier layer 212, which may be surrounded by a layer of etch-resistant material (e.g., an etch-stop layer 211). In some embodiments, the diffusion barrier 212 may be a metal- or copper-diffusion barrier (e.g., a conductive material to reduce or prevent the diffusion of metal or copper from WL 250 into the gate electrode 214 while still maintaining an electrical connection between the WL 250 and the gate electrode 214) on the WL 250 such as TaN, tantalum (Ta), titanium zirconium nitride (e.g., TiXZr1-XN, such as X=0.53), titanium nitride (e.g., TiN), titanium tungsten (TiW), combination (such as a stack structure of TaN on Ta), or the like. For instance, the diffusion barrier 212 can include a single- or multilayer structure including a compound of tantalum (Ta) and nitrogen (n), such as TaN or a layer of TaN on a layer of Ta. In some embodiments, a layer of an etch-resistant material (e.g., the etch-stop 211) such as silicon nitride or silicon carbide may be formed over the WL 250 with vias for a metal (or copper) diffusion barrier film 212 such as TaN or a TaN/Ta stack. The gate electrode 214 can be a conductive material on the diffusion barrier 212, such as metal, conductive metal oxide or nitride, or the like. For example, in one embodiment, the gate electrode 214 may be titanium nitride (TiN). In another embodiment, the gate electrode 214 may be tungsten (W).

The channel layer 218 can be in contact with the BL 240 (e.g., at a first S/D region of the channel layer 218, e.g., a drain region) and with the storage node 230 (e.g., at a second S/D region of the channel layer 218, e.g., a source region, with a semiconducting channel region of the access TFT 210 being between the first S/D region and the second S/D region). In some embodiments, such a channel region may include only majority carriers in the thin film. Accordingly, the channel layer 218 may require a relatively high bias (as e.g., supplied by the WL 250, diffusion barrier film 212, and gate electrode 214) to activate.

Example IC Devices with Backend Memory and Air Gaps in Upper Metal Layers

FIG. 4 provides a schematic illustration of an IC device 400 with backend memory and air gaps in upper metal layers, according to some embodiments of the present disclosure.

As shown in FIG. 4 , the IC device 400 may include a support structure 410, an FEOL layer 420 and one or more BEOL layers 430 above the FEOL layer 420. As also shown in FIG. 4 , the BEOL layers 430 may further include a backend memory layer 432 and at least one air gap layer 434, so that the backend memory layer 432 is between the FEOL layer 420 and the air gap layer 434, and the FEOL layer 420 is between the support structure 410 and the one or more BEOL layers 430.

The FEOL layer 420 may include a plurality of frontend/FEOL devices, e.g., FEOL transistors such as FinFETs, nanowire transistors, nanoribbon transistors, etc. In some embodiments, some or all of the FEOL transistors may be implemented as transistors with back-side contacts. In some embodiments, some or all of the FEOL transistors may be implemented as transistors with front-side contacts. In general, a transistor is described as a transistor with front-side contacts if both S/D contacts of the transistor are on one side of a channel material of the transistor, above the channel material of the transistor. On the other hand, a transistor is described as a transistor with back-side contacts if either both S/D contacts of the transistor are below the channel material of the transistor or if one S/D contact is on one side with respect to the channel material (e.g., above the channel material) and the other S/D contact is on the opposite side (e.g., below the channel material).

The backend memory layer 432 of the BEOL layers 430 may include at least one layer of backend memory, e.g., a memory array with a plurality of 1T-1C memory cells as described herein, e.g., memory cells 100/200 as described herein, or a stack of such layers/arrays. In addition, the BEOL layers 430 may further include a plurality of backend interconnects electrically coupled to (e.g., in electrically conductive contact with at least portions of) one or more of the plurality of FEOL devices of the FEOL layer 420 and/or one or more of the plurality of memory cells of the backend memory layer 432. The air gap layer 434 may be a layer of such backend interconnects (e.g., conductive lines) with air gaps between at least some pairs of adjacent interconnects.

In some embodiments, the FEOL transistors implemented in the FEOL layer 420 may be a part of compute logic, e.g., to serve as a memory peripheral circuit for the memory arrays implemented in the one or more BEOL layers 430. For example, the FEOL transistors may be responsible for compute logic functionality related to read/write operations with respect to the data stored in the memory cells that may be implemented in the one or more BEOL layers 430. To that end, some of the FEOL transistors of the FEOL layer 420 may be part of one or more input/output (I/O) ICs (e.g., a memory peripheral circuit) configured to control (e.g., control access (read/write), store, refresh) the memory cells implemented in the IC device 400 (e.g., memory cells implemented in the one or more BEOL layers 430). In some embodiments, some of the FEOL transistors of the FEOL layer 420 may be part of high-performance compute logic, configured to perform various operations with respect to data stored in the memory cells implemented in the IC device 400 (e.g., arithmetic and logic operations, pipelining of data from one or more of the memory arrays implemented in the IC device 400, and possibly also data from external devices/chips). In some embodiments of the IC device 400, the compute logic may be provided in the FEOL 420 and in one or more lowest metal layer of the BEOL layers 430, while one or more backend memory arrays may be provided in higher layers of the BEOL layers 430. In other embodiments of the IC device 400, the compute logic described with reference to the FEOL layer 420 may be provided above the FEOL layer 420 (e.g., in the one or more BEOL layers 430), in between memory layers of the BEOL layers 430, or combined with the memory layers of the one or more BEOL layers 430.

Various BEOL layers of the one or more BEOL layers 430 may be/include metal layers of a metallization stack of the IC device 400. Various metal layers of the BEOL may be used to interconnect the various inputs and outputs of the logic devices in the compute logic of the FEOL layer 420 and/or of the memory cells in the memory layers of the one or more BEOL layers 430. Generally speaking, each of the metal layers of the one or more BEOL layers 430 may include a via portion and a trench/interconnect portion. The trench portion of a metal layer is configured for transferring signals and power along electrically conductive (e.g., metal) lines (also sometimes referred to as “trenches”) extending in the x-y plane (e.g., in the x or y directions), while the via portion of a metal layer is configured for transferring signals and power through electrically conductive vias extending in the z-direction, e.g., to any of the adjacent metal layers above or below. Accordingly, vias connect metal structures (e.g., metal lines or vias) from one metal layer to metal structures of an adjacent metal layer. While referred to as “metal” layers, various layers of the one or more BEOL layers 430 may include only certain patterns of conductive metals, e.g., copper (Cu), aluminum (Al), tungsten (W), or cobalt (Co), or metal alloys, or more generally, patterns of an electrically conductive material, formed in an insulating medium such as an ILD. The insulating medium may include any suitable ILD materials such as silicon oxide, carbon-doped silicon oxide, silicon carbide, silicon nitride, aluminum oxide, and/or silicon oxynitride.

As shown in FIG. 4 , the FEOL layer 420 may be provided over the support structure 410, e.g., a semiconductor support structure, such as a substrate, a die, a wafer or a chip. Such a support structure may, e.g., be the wafer 2000 of FIG. 7A, discussed below. Such a semiconductor support structure may be a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride or gallium antimonide, or other combinations of group III-V materials (i.e., materials from groups III and V of the periodic system of elements), group II-VI (i.e., materials from groups II and IV of the periodic system of elements), or group IV materials (i.e., materials from group IV of the periodic system of elements). In some embodiments, the substrate may be non-crystalline. In some embodiments, the substrate may be a printed circuit board (PCB) substrate. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which the FEOL layer 420 as described herein may be built falls within the spirit and scope of the present disclosure. In various embodiments, channel materials of the transistors of the FEOL layer 420 may include, or may be formed upon, any such substrate material.

In some embodiments, the channel material of the FEOL transistors of the FEOL layer 420 may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, the channel material of the FEOL transistors may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the channel material of the FEOL transistors may include a combination of semiconductor materials where one semiconductor material may be used for the channel portion and another material, sometimes referred to as a “blocking material,” may be used between the channel portion and the support structure over which the FEOL transistors are provided. In some embodiments, the channel material of the FEOL transistors may include a monocrystalline semiconductor, such as silicon (Si) or germanium (Ge). In some embodiments, the channel material of the FEOL transistors may include a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb).

For some example N-type transistor embodiments (i.e., for the embodiments where a given FEOL transistor is an NMOS), the channel portion of the FEOL transistor may advantageously include a III-V material having a high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, the channel portion may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some In_(x)Ga_(1-x)As fin embodiments, In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In_(0.7)Ga_(0.3)As). In some embodiments with highest mobility, the channel portion may be an intrinsic III-V material, i.e., a III-V semiconductor material not intentionally doped with any electrically active impurity. In alternate embodiments, a nominal impurity dopant level may be present within the channel portion, for example to further fine-tune a threshold voltage Vt, or to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel portion of the FEOL transistors may be relatively low, for example below 10¹⁵ dopant atoms per cubic centimeter (cm⁻³), and advantageously below 10¹³ cm⁻³.

For some example P-type transistor embodiments (i.e., for the embodiments where a given FEOL transistor is a PMOS), the channel portion of the FEOL transistor may advantageously be a group IV material having a high hole mobility, such as, but not limited to Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel portion may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7. In some embodiments with highest mobility, the channel portion may be intrinsic III-V (or IV for P-type devices) material and not intentionally doped with any electrically active impurity. In alternate embodiments, one or more a nominal impurity dopant level may be present within the channel portion of the FEOL transistors, for example to further set a threshold voltage (Vt), or to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel portion is relatively low, for example below 10¹⁵ cm⁻³, and advantageously below 10¹³ cm⁻³.

While the FEOL layer 420 may originally be provided over a semiconductor support structure as described above, in some embodiments, such a semiconductor support structure may subsequently be removed to expose the back-side portions of the FEOL devices of the FEOL layer 420 so that a back-side power delivery structure may be provided at the back side of the FEOL layer 420 (thus, the one or more BEOL layers 430 are provided at the front side of the FEOL layer 420, the back-side power delivery structure is provided at the back side of the FEOL layer 420, and the support structure 410 shown in FIG. 2 is, or includes, such a back-side power delivery structure). The back-side power delivery structure 410 may include a plurality of interconnects (i.e., conductive lines and vias) configured to provide power to one or more devices (e.g., logic transistors) of the FEOL layer 420 and to one or more devices (e.g., backend memory cells) of the one or more BEOL layers 430. In some embodiments, the back-side power delivery structure 410 may further include various IC components (e.g., capacitors, inductors, resistors, etc.) for reducing the parasitic effects of the IC device 400, e.g., for reducing parasitic effects associated with the interconnects used for power delivery.

FIG. 5 provides a cross-sectional side view of an example IC device 500 with backend memory and air gaps in upper metal layers, according to some embodiments of the present disclosure. A number of elements labeled in FIG. 5 and in at least some of the subsequent figures with reference numerals are illustrated in these figures with different patterns, with a legend showing the correspondence between the reference numerals and patterns being provided at the bottom of each drawing page containing these figures. For example, the legend illustrates that FIG. 5 uses different patterns to show a semiconductor material 502, frontend transistors 504, an ILD material 506, interconnects 508, etc. Furthermore, although a certain number of a given element may be illustrated in FIG. 5 and in at least some of the subsequent figures, this is also simply for ease of illustration, and more, or less, than that number may be included in an IC device according to various embodiments of the present disclosure. Still further, FIG. 5 is intended to show relative arrangements of various elements in an example IC device with backend memory and air gaps in upper metal layers, and that various IC devices with backend memory and air gaps in upper metal layers, or portions thereof, may include other elements or components that are not illustrated (e.g., any further materials, such as spacer materials that may surround the gate stack of the transistors, etch-stop materials, etc.).

The IC device 500 may be an example implementation of the IC device 400, which is indicated in FIG. 5 by labeling the support structure 410, the FEOL layer 420, and the BEOL layers 430 on the left side of FIG. 5 . As shown in FIG. 5 , in some embodiments, the support structure 410 may include a semiconductor material 502, upon which frontend transistors 504 may be provided. The semiconductor material 502 may be an upper portion of any of the semiconductor support structures as described above. The details of the frontend transistors 504 are not shown in FIG. 5 because various architectures of such transistors are known and the frontend transistors 504 may include a transistor of any architecture as known in the art. The channel regions of the frontend transistors 504 may include the semiconductor material 502. Although not specifically shown in FIG. 5 , in some embodiments, the semiconductor material 502 may be included only in a portion of the support structure 410, e.g., as a channel material of the frontend transistors 504, and the rest of the semiconductor material of the original support structure upon which the frontend transistors 504 were built may be removed and replaced by, e.g., a back-side power delivery structure or a non-semiconductor supports structure (e.g., a glass support structure).

FIG. 5 illustrates an ILD material 506 and a plurality of interconnects 508 above the frontend transistors 504. A portion of the ILD material 506 directly above and surrounding portions of the frontend transistors 504, and one or more of the interconnects 508 in that portion of the ILD material 506 may be seen as a part of the FEOL layer 420, whereas everything above may be seen as a part of the BEOL layers 430, as labeled in FIG. 5 . In particular, the BEOL layers 430 may include a metallization stack of a plurality of metal layers labeled in FIG. 5 as a metal layer 1 (M1), a metal layer 2 (M2), and so on. Although not specifically shown in FIG. 5 , a layer of an etch-stop (ES) material may be present between at least portions of adjacent metal layers of the BEOL layers 430, as known in the art.

In some embodiments, even when only a single layer of backend memory cells is implemented, the backend memory layer 432 may occupy a plurality of consecutive metal layers of the metallization stack of the IC device 500. This is shown in FIG. 5 with the backend memory layer 432 being in the metal layers M5, M6, and M7. In particular, FIG. 5 illustrates access transistors 510, S/D contacts 512 for the access transistors 510, and capacitors 514 (only one of which is labeled in FIG. 5 in order to not clutter the drawing even though two capacitors 514 are shown). FIG. 5 further provides a label for a memory cell 520, illustrated in FIG. 5 within a dashed rectangular contour, that includes one access transistor 510 and one capacitor 514, coupled to one of the S/D contacts 512 of the access transistor 510. Thus, the memory cell 520 is an example of a 1T-1C memory cell, e.g., the memory cell 100 as described above, where the access transistor 510 is an example of the access transistor 110, and the capacitor 514 is an example of the capacitor 120, described above. Two such memory cells 520 are shown in FIG. 5 , but only one is labeled with reference numerals in order to not clutter the drawing. The memory cell 520 may be a backend memory cell according to any of the embodiments described above, e.g., an eDRAM memory cell as explained with reference to FIGS. 1-3 . For example, as shown in FIG. 5 , in some embodiments of the memory cell 520, one of the interconnects 508 in a metal layer M5 may form a WL such as the WL 250, described above, while the access transistor 510, a storage node such as the storage node 230, and a BL such as the BL 240 may be formed in a metal layer M6 of the BEOL 430 (i.e., the metal layer directly above the metal layer M5), and the capacitor 514 may then be formed in a metal layer M7 (i.e., the metal layer directly above the metal layer M6). FIG. 5 further illustrates a PL such as the PL 160, described above, which may be coupled to one of the interconnects 508 in the metal layer M7. In other embodiments of the IC device 500, backend memory with memory cells as the memory cell 520 may be implemented in other metal layers of the BEOL layers 430, any number of memory cells 520 may be included in a given layer/array of backend memory cells, and multiple layers of backend memory cells such as the memory cell 520 may be stacked over one another, thus implementing three-dimensional (3D) stacked backend memory.

FIG. 5 further illustrates the air gap layer 434 as another layer of the BEOL layers 430, above the backend memory layer 432, as a metal layer that may include a plurality of interconnects 508 with air gaps 534 in between adjacent pairs (only one of the air gaps 534 is labeled in FIG. 5 in order to not clutter the drawing). For example, in some embodiments, the air gap layer 434 may be a part of a metal layer M9, as shown in FIG. 5 . However, in other embodiments, the air gap layer 434 may be included in other metal layers of the BEOL layers 430 and may include any number of the air gaps 534. In some embodiments, the air gap layer 434 may be provided above all layers of the backend memory, as is shown in FIG. 5 , i.e., in the upper metal layer(s) of the BEOL layers 430. As such, an average pitch (e.g., a center-to-center distance) of the interconnects 508 in the air gap layer 434 may be relatively large, e.g., at least about 200 nanometers, including all values and ranges therein, e.g., at least about 300 nanometers or at least about 350 nanometers. Further details of the air gaps 534 may be explained with reference to FIGS. 6A-6D.

IC devices with backend memory and air gaps in upper metal layers, as described herein, may be fabricated using any suitable techniques, e.g., subtractive, additive, damascene, dual damascene, etc. Some of such technique may include suitable deposition and patterning techniques. As used herein, “patterning” may refer to forming a pattern in one or more materials using any suitable techniques (e.g., applying a resist, patterning the resist using lithography, and then etching the one or more material using dry etching, wet etching, or any appropriate technique).

FIGS. 6A-6D provide cross-sectional side views at different stages of fabricating an IC device with backend memory and air gaps in upper metal layers (e.g., the IC device 400 or the IC device 500), according to some embodiments of the present disclosure. The example fabrication method shown in FIGS. 6A-6D may include other operations not specifically shown in FIGS. 6A-6D, such as various cleaning or planarization operations as known in the art. For example, in some embodiments, any of the layers of the IC device may be cleaned prior to, after, or during any of the processes of the fabrication method described herein, e.g., to remove oxides, surface-bound organic and metallic contaminants, as well as subsurface contamination. In some embodiments, cleaning may be carried out using e.g., a chemical solutions (such as peroxide), and/or with ultraviolet (UV) radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g., using hydrofluoric acid (HF)). In another example, the top surfaces of the IC devices described herein may be planarized prior to, after, or during any of the processes of the fabrication method described herein, e.g., to remove overburden or excess materials. In some embodiments, planarization may be carried out using either wet or dry planarization processes, e.g., planarization be a chemical mechanical planarization (CMP), which may be understood as a process that utilizes a polishing surface, an abrasive and a slurry to remove the overburden and planarize the surface.

The fabrication method may begin with a process 602, shown in FIG. 6A, that includes providing a metal layer 612 in which air gaps are to be formed. The metal layer 612 may be an example of the air gap layer 434. Layers below the metal layer 612 are not shown in FIGS. 6A-6D in order to not clutter the drawings, but they would be present there similar to how they are illustrated in, e.g., FIG. 5 . Thus, before the fabrication method proceeds with processes as shown in FIGS. 6A-6D, it first includes providing, over a semiconductor material (e.g., the semiconductor material 502), a frontend layer (e.g., the FEOL 420), comprising a plurality of frontend devices (e.g., the frontend transistors 504), and then providing, over the frontend layer, a layer that includes a plurality of backend memory cells (e.g., the backend memory cells 520), using any of the processes as known in the art. The process 602 then includes providing, over the layer that includes the plurality of backend memory cells (e.g., over the backend memory layer 432), a layer of an ILD material 614 (e.g., the ILD material 506, as described above), and forming a plurality of conductive lines 616 (four of which are shown for the example of FIGS. 6A-6D) in the ILD material 614. As shown in FIG. 6A, in some embodiments, the conductive lines 616 may include an optional liner 618 and an electrically conductive fill material 620. If included in the interconnects 616, the liner 618 may be an adhesion liner and/or a barrier liner. For example, the liner 618 may be a liner having one or more of tantalum, tantalum nitride, titanium nitride, tungsten carbide, cobalt, etc. The electrically conductive fill material 620 may include one or more of copper, tungsten, aluminum, ruthenium, cobalt, etc. (e.g., in proportions of between 1:1 to 1:100), or any of the electrically conductive materials described above. In the liner 618 and/or in the electrically conductive fill material 620, any of the individual materials (e.g., any of the examples listed above) may be included in the amount of between about 1% and 75%, e.g., between about 5% and 50%, indicating that these materials are included by intentional alloying of materials, in contrast to potential accidental doping or impurities being included, which would be less than about 0.1% for any of these metals. FIG. 6A also illustrates that an ES material 622 may be provided directly below and/or directly above the ILD material 614. In some embodiments, the ES material 622 may include silicon and nitrogen (e.g., silicon nitride), silicon and carbon (e.g., silicon carbide), or a material that includes silicon, nitrogen, and carbon. The ES material 622 may include any material that is sufficiently etch-selective with respect to the surrounding materials, where, as known in the art, two materials are described as being “sufficiently etch-selective” if etchants used to etch one material do not substantially etch the other material, and possibly vice versa.

In some embodiments, the interconnects 616 may be metal lines. In some embodiments, the interconnects 616 may have an average pitch 624 (e.g., a center-to-center distance) of the interconnects 508 in the air gap layer 434 may be relatively large, e.g., at least about 200 nanometers, including all values and ranges therein, e.g., at least about 300 nanometers or at least about 350 nanometers. In some embodiments, an average width of the interconnects 616 may be about half of the average pitch 624.

The ILD material 614 may be deposited in the process 602 using any suitable deposition techniques, such as spin-coating, dip-coating, atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD) (e.g., evaporative deposition, magnetron sputtering, or e-beam deposition). If subtractive fabrication is used to form the interconnects 616, openings in the ILD material 614 for the future interconnects 616 may be formed using any suitable etching technique such as e.g., radio frequency (RF) reactive ion etch (RIE) or inductively coupled plasma (ICP) RIE), possibly in combination with lithography (e.g., photolithography or electron-beam lithography) to define the locations and the sizes of these openings. The liner 618 and the electrically conductive fill material 620 may then be deposited within the openings in the ILD material 614 using any suitable deposition techniques, such as ALD, CVD, or PVD. In particular, the liner 618 may be deposited as a conformal layer to line sidewalls and bottoms of the openings for the interconnects 616, e.g., using a conformal deposition technique such as ALD.

The fabrication method may then proceed with a process 604, shown in FIG. 6B, that includes removing the upper ES layer 622, if it was deposited in the process 602, and recessing some of the ILD material 614. In some embodiments, the ILD material 614 may be recessed so that it is substantially aligned with the bottoms of the interconnects 616, as shown in FIG. 6B. The ILD material 614 may be recessed in the process 604 using any suitable etching technique, such as any of the ones described above. In some embodiments, timed etch may be used to control the depth of the recess of the process 604.

The fabrication method may then proceed with a process 606, shown in FIG. 6C, that includes depositing a layer of a sealing material 626 over all of the surfaces exposed by recessing the ILD material 614 in the process 604. In some embodiments, the sealing material 626 may include one or more of a material including silicon and nitrogen (e.g., SiN), a material including silicon and carbon (e.g., SiC), a material including silicon, oxygen, and nitrogen (e.g., SiON), a material including silicon, carbon, and hydrogen (e.g., SiCN), a material including hafnium and oxygen (e.g., HfO₂), a material including aluminum and oxygen (e.g., Al₂O₃), or any combination of materials that is found to be hermetic during further processing. In some embodiments, the sealing material 626 may be deposited using any suitable conformal deposition technique such as ALD. The sealing material 626 may include any suitable material to protect the electrically conductive material(s) of the interconnects 616 from air, moisture, etc. In some embodiments, a thickness of the sealing material 626 may be between about 2 and 10 nanometers, including all values and ranges therein, e.g., around about 4 nanometers.

The fabrication method may further include a process 608, shown in FIG. 6D, in which a second ILD material 628 is deposited so that air gaps 634 are formed between adjacent ones of the interconnects 616. The second ILD material 628 may include any of the materials of the ILD material 614 and, in various embodiments, material compositions of these two ILD materials may, but do not have to be, substantially the same. The deposition process by which the second ILD material 628 may be deposited may be such as to minimize deposition of the second ILD material 628 within the air gaps 634. For example, in some embodiments, substantially none of the second ILD material 628 may be present in the air gaps 634. In other embodiments, some of the second ILD material 628 may be present on sidewalls and bottoms of the air gaps 634, e.g., as is shown in an inset 642 provided in FIG. 6D, illustrating an alternative view of a portion of the IC device within a dashed contour 640. Thus, in such embodiments, some of the second ILD material 628 may be present on sidewalls of the adjacent interconnects 616, forming the sidewalls of the air gaps 634, and/or some of the second ILD material 628 may be present at the bottom of the recess in the ILD material 614, forming the bottoms of the air gaps 634, as is shown in the inset 642. In some embodiments, before depositing the second ILD material 628, another layer of an ES material may be deposited. In such embodiments, such a layer of the ES material may be deposited in such a way as to form the air gaps 634, and then the second ILD material 628 may be deposited, as is shown with an ES material 630 of an inset 644 provided in FIG. 6D, illustrating another alternative view of a portion of the IC device within the dashed contour 640. In some embodiments, substantially none of the ES material 630 may be present in the air gaps 634. In other embodiments, some of the ES material 630 may be present on sidewalls and bottoms of the air gaps 634, e.g., as is shown in the inset 644. In some such embodiments, some of the second ILD material 628 may be present on sidewalls and bottoms of the air gaps 634, e.g., as is shown in the inset 644, but, in other such embodiments, substantially no second ILD material 628 may be present on sidewalls and bottoms of the air gaps 634.

In some embodiments, an average width of the air gaps 634, e.g., measured at about half of a height of the air gaps 634, as shown with a distance 632 in FIG. 6D, may be at least about 70 nanometers, including all values and ranges therein, e.g., at least about 80 nanometers or at least about 100 nanometers. In some embodiments, the air gaps 634 may have an obelisk shape, as shown in FIG. 6D, due to the pinching in the deposition of the material that seals the air gaps 634 (e.g., the second ILD material 628 or the ES material 630). In some embodiments, the air gaps 634 may be such that their width decreases at distances successively further away from the FEOL layer 420 (i.e., the air gaps 634 become narrower as they get closer to their tops, until they are pinched at the tops). The air gaps 634 may be an example of the air gaps 534, described above, and the interconnects 616 as shown in FIG. 6D may be an example of the interconnects 508 of the air gap layer 434, described above.

Example Devices and Systems

IC devices with backend memory and air gaps in upper metal layers as disclosed herein may be included in any suitable electronic device. FIGS. 7-11 illustrate various examples of devices and components that may include one or more IC devices with backend memory and air gaps in upper metal layers as disclosed herein.

FIGS. 7A-7B are top views of a wafer 2000 and dies 2002 that may include one or more IC devices with backend memory and air gaps in upper metal layers in accordance with any of the embodiments disclosed herein. In some embodiments, the dies 2002 may be included in an IC package, in accordance with any of the embodiments disclosed herein. For example, any of the dies 2002 may serve as any of the dies 2256 in an IC package 2200 shown in FIG. 9 . The wafer 2000 may be composed of semiconductor material and may include one or more dies 2002 having IC structures formed on a surface of the wafer 2000. Each of the dies 2002 may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., IC devices that include backend memory and air gaps in upper metal layers as described herein). After the fabrication of the semiconductor product is complete (e.g., after manufacture of one or more IC devices with backend memory and air gaps in upper metal layers as described herein, e.g., any embodiment of the IC devices 400/500, described herein), the wafer 2000 may undergo a singulation process in which each of the dies 2002 is separated from one another to provide discrete “chips” of the semiconductor product. In particular, devices that include backend memory and air gaps in upper metal layers as disclosed herein may take the form of the wafer 2000 (e.g., not singulated) or the form of the die 2002 (e.g., singulated). The die 2002 may include one or more transistors (e.g., one or more transistors of the FEOL layer 420 and one or more transistors of the backend memory of the BEOL layers 430, as described herein and/or one or more FEOL transistors 2140 of FIG. 8 , discussed below), one or more memory cells (e.g., one or more 1T-1C memory cells as described herein), and/or supporting circuitry (e.g., one or more interconnects as described herein) to route electrical signals to the transistors and/or the memory cells, as well as any other IC components. In some embodiments, the wafer 2000 or the die 2002 may implement or include a memory device, a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 2002. For example, a memory array formed by multiple memory cells in a given layer may be formed on a same die 2002 as a processing device (e.g., the processing device 2402 of FIG. 11 ) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

FIG. 8 is a cross-sectional side view of one side of an IC device 2100 that may include backend memory and air gaps in upper metal layers in accordance with any of the embodiments disclosed herein. For example, the IC device 2100 may be an example of the IC devices 400/500, described above. In particular, the backend memory layer 632 and the air gap layer 634 as described herein may be implemented in any of the BEOL layers of the IC device 2100, e.g., in any of the interconnect layers 2106-2110 shown in FIG. 8 . Because there are various possibilities where such backend memory layer 632 and the air gap layer 634 may be integrated in the IC device 2100, the backend memory layer 632 and the air gap layer 634 are not specifically shown in FIG. 8 . In some embodiments, the IC device 2100 may serve as any of the dies 2256 in the IC package 2300.

As shown in FIG. 8 , the IC device 2100 may be formed on a substrate 2102 (e.g., the wafer 2000 of FIG. 7A) and may be included in a die (e.g., the die 2002 of FIG. 7B). The substrate 2102 may include any material that may serve as a foundation for an IC device 2100. The substrate 2102 may be a semiconductor substrate and may include any of the examples described above with reference to the support structure 410. Although a few examples of the substrate 2102 are described here, any material or structure that may serve as a foundation upon which an IC device 2100 may be built falls within the spirit and scope of the present disclosure. The substrate 2102 may be part of a singulated die (e.g., the die 2002 of FIG. 7B) or a wafer (e.g., the wafer 2000 of FIG. 7A).

The IC device 2100 may include one or more device layers 2104 disposed on the substrate 2102. The device layers 2104 provide one example of one or more layers with the logic devices of the FEOL layer 420, described above. The device layer 2104 may include features of one or more transistors 2140 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 2102. The transistors 2140 provide one example of any of the transistors of the FEOL layer 420, described above. The device layer 2104 may include, for example, one or more S/D regions 2120, a gate 2122 to control current flow in the transistors 2140 between the S/D regions 2120, and one or more S/D contacts 2124 to route electrical signals to/from the S/D regions 2120. The transistors 2140 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like.

Each transistor 2140 may include a gate 2122 formed of at least two layers, a gate dielectric layer and a gate electrode layer. Generally, the gate dielectric layer of a transistor 2140 may include one layer or a stack of layers and may include any of the materials described above with reference to the gate dielectric 216. In some embodiments, an annealing process may be carried out on the gate dielectric of the gate 2122 to improve its quality when a high-k material is used.

The gate electrode may be formed on the gate dielectric and may include at least one P-type work function metal or N-type work function metal, depending on whether the transistor 2140 is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. The gate electrode of the gate 2122 may include any of the materials described above with reference to the gate electrode 214.

In some embodiments, when viewed as a cross-section of the transistor 2140 along the source-channel-drain direction, the gate electrode of the gate 2122 may include a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may include a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. In some embodiments, the gate electrode may include a V-shaped structure (e.g., when the fin of a FinFET does not have a “flat” upper surface, but instead has a rounded peak).

In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

The S/D regions 2120 may be formed within the substrate 2102, e.g., adjacent to the gate of each transistor 2140. The S/D regions 2120 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate 2102 to form the S/D regions 2120. An annealing process that activates the dopants and causes them to diffuse farther into the substrate 2102 may follow the ion-implantation process. In the latter process, the substrate 2102 may first be etched to form recesses at the locations of the S/D regions 2120. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 2120. In some implementations, the S/D regions 2120 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 2120 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 2120.

Various transistors 2140 are not limited to the type and configuration depicted in FIG. 8 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors (e.g., FinFETs, nanowire, or nanoribbon transistors), or a combination of both.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the transistors 2140 of the device layer 2104 through one or more interconnect layers disposed on the device layer 2104 (illustrated in FIG. 8 as interconnect layers 2106-2110). For example, electrically conductive features of the device layer 2104 (e.g., the gate 2122 and the S/D contacts 2124) may be electrically coupled with the interconnect structures 2128 of the interconnect layers 2106-2110. The one or more interconnect layers 2106-2110 may form an ILD stack 2119 of the IC device 2100. The interconnect structures 2128 are examples of the interconnects 508/616, described herein. The ILD stack 2119 of the IC device 2100 is an example of the metallization stack of the BEOL layers 430, described herein. The interconnect layers 2106-2110 are examples of metal layers M1, M2, and so on, described herein.

The interconnect structures 2128 may be arranged within the interconnect layers 2106-1210 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 2128 depicted in FIG. 8 ). Although a particular number of interconnect layers 2106-1210 is depicted in FIG. 8 , embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures 2128 may include trench structures 2128 a (sometimes referred to as “lines”) and/or via structures 2127B (sometimes referred to as “holes”) filled with an electrically conductive material such as a metal. The trench structures 2128 a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 2102 upon which the device layer 2104 is formed. For example, the trench structures 2128 a may route electrical signals in a direction in and out of the page from the perspective of FIG. 8 . The via structures 2127B may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 2102 upon which the device layer 2104 is formed. In some embodiments, the via structures 2127B may electrically couple trench structures 2128 a of different interconnect layers 2106-2110 together.

The interconnect layers 2106-2110 may include a dielectric material 2126 disposed between the interconnect structures 2128, as shown in FIG. 8 . In some embodiments, the dielectric material 2126 disposed between the interconnect structures 2128 in different ones of the interconnect layers 2106-2110 may have different compositions; in other embodiments, the composition of the dielectric material 2126 between different interconnect layers 2106-2110 may be the same. The dielectric material 2126 may include any of the insulator/dielectric materials described above.

A first interconnect layer 2106 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 2104. In some embodiments, the first interconnect layer 2106 may include trench structures 2128 a and/or via structures 21273, as shown. The trench structures 2128 a of the first interconnect layer 2106 may be coupled with contacts (e.g., the S/D contacts 2124) of the device layer 2104.

A second interconnect layer 2108 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 2106. In some embodiments, the second interconnect layer 2108 may include via structures 21273 to couple the trench structures 2128 a of the second interconnect layer 2108 with the trench structures 2128 a of the first interconnect layer 2106. Although the trench structures 2128 a and the via structures 21273 are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 2108) for the sake of clarity, the trench structures 2128 a and the via structures 21273 may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual damascene process) in some embodiments.

A third interconnect layer 2110 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 2108 according to similar techniques and configurations described in connection with the second interconnect layer 2108 or the first interconnect layer 2106.

The interconnect layers 2106-2110 may be the metal layers M1-M3, described above. Further metal layers may be present in the IC device 2100, as also described above.

FIG. 9 is a side, cross-sectional view of an example IC package 2200 that may include one or more IC devices with backend memory and air gaps in upper metal layers in accordance with any of the embodiments disclosed herein. In some embodiments, the IC package 2200 may be a system-in-package (SiP).

The package substrate 2252 may be formed of a dielectric material (e.g., a ceramic, a buildup film, an epoxy film having filler particles therein, etc.), and may have conductive pathways extending through the dielectric material between the face 2272 and the face 2274, or between different locations on the face 2272, and/or between different locations on the face 2274. These conductive pathways may take the form of any of the interconnect structures 2128 discussed above with reference to FIG. 8 .

The package substrate 2252 may include conductive contacts 2263 that are coupled to conductive pathways 2262 through the package substrate 2252, allowing circuitry within the dies 2256 and/or the interposer 2257 to electrically couple to various ones of the conductive contacts 2264 (or to other devices included in the package substrate 2252, not shown).

The IC package 2200 may include an interposer 2257 coupled to the package substrate 2252 via conductive contacts 2261 of the interposer 2257, first-level interconnects 2265, and the conductive contacts 2263 of the package substrate 2252. The first-level interconnects 2265 illustrated in FIG. 9 are solder bumps, but any suitable first-level interconnects 2265 may be used. In some embodiments, no interposer 2257 may be included in the IC package 2200; instead, the dies 2256 may be coupled directly to the conductive contacts 2263 at the face 2272 by first-level interconnects 2265.

The IC package 2200 may include one or more dies 2256 coupled to the interposer 2257 via conductive contacts 2254 of the dies 2256, first-level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive pathways (not shown) through the interposer 2257, allowing circuitry within the dies 2256 to electrically couple to various ones of the conductive contacts 2261 (or to other devices included in the interposer 2257, not shown). The first-level interconnects 2258 illustrated in FIG. 9 are solder bumps, but any suitable first-level interconnects 2258 may be used. As used herein, a “conductive contact” may refer to a portion of electrically conductive material (e.g., metal) serving as an interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket).

In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first-level interconnects 2265, and a mold compound 2268 may be disposed around the dies 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the mold compound 2268. Example materials that may be used for the underfill material 2266 and the mold compound 2268 are epoxy mold materials, as suitable. Second-level interconnects 2270 may be coupled to the conductive contacts 2264. The second-level interconnects 2270 illustrated in FIG. 9 are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects 22770 may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnects 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference to FIG. 10 .

The dies 2256 may take the form of any of the embodiments of the die 2002 discussed herein (e.g., may include any of the embodiments of the IC device 2100). In embodiments in which the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The dies 2256 may include circuitry to perform any desired functionality. For example, one or more of the dies 2256 may be logic dies (e.g., silicon-based dies), and one or more of the dies 2256 may be memory dies (e.g., high bandwidth memory), including embedded memory dies as described herein. In some embodiments, any of the dies 2256 may include one or more IC devices with backend memory and air gaps in upper metal layers, e.g., as discussed above; in some embodiments, at least some of the dies 2256 may not include any IC devices with backend memory and air gaps in upper metal layers.

The IC package 2200 illustrated in FIG. 9 may be a flip chip package, although other package architectures may be used. For example, the IC package 2200 may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are illustrated in the IC package 2200 of FIG. 9 , an IC package 2200 may include any desired number of the dies 2256. An IC package 2200 may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first face 2272 or the second face 2274 of the package substrate 2252, or on either face of the interposer 2257. More generally, an IC package 2200 may include any other active or passive components known in the art.

FIG. 10 is a cross-sectional side view of an IC device assembly 2300 that may include components having one or more IC devices with backend memory and air gaps in upper metal layers in accordance with any of the embodiments disclosed herein. The IC device assembly 2300 includes a number of components disposed on a circuit board 2302 (which may be, e.g., a motherboard). The IC device assembly 2300 includes components disposed on a first face 2340 of the circuit board 2302 and an opposing second face 2342 of the circuit board 2302; generally, components may be disposed on one or both faces 2340 and 2342. In particular, any suitable ones of the components of the IC device assembly 2300 may include any of one or more IC devices with backend memory and air gaps in upper metal layers in accordance with any of the embodiments disclosed herein; e.g., any of the IC packages discussed below with reference to the IC device assembly 2300 may take the form of any of the embodiments of the IC package 2200 discussed above with reference to FIG. 9 (e.g., may include one or more IC devices with backend memory and air gaps in upper metal layers provided on a die 2256).

In some embodiments, the circuit board 2302 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2302. In other embodiments, the circuit board 2302 may be a non-PCB substrate.

The IC device assembly 2300 illustrated in FIG. 10 includes a package-on-interposer structure 2336 coupled to the first face 2340 of the circuit board 2302 by coupling components 2316. The coupling components 2316 may electrically and mechanically couple the package-on-interposer structure 2336 to the circuit board 2302, and may include solder balls (e.g., as shown in FIG. 10 ), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure 2336 may include an IC package 2320 coupled to an interposer 2304 by coupling components 2318. The coupling components 2318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2316. The IC package 2320 may be or include, for example, a die (the die 2002 of FIG. 7B), an IC device (e.g., the IC device 2100 of FIG. 8 ), or any other suitable component. In particular, the IC package 2320 may include one or more IC devices with backend memory and air gaps in upper metal layers as described herein. Although a single IC package 2320 is shown in FIG. 10 , multiple IC packages may be coupled to the interposer 2304; indeed, additional interposers may be coupled to the interposer 2304. The interposer 2304 may provide an intervening substrate used to bridge the circuit board 2302 and the IC package 2320. Generally, the interposer 2304 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 2304 may couple the IC package 2320 (e.g., a die) to a BGA of the coupling components 2316 for coupling to the circuit board 2302. In the embodiment illustrated in FIG. 10 , the IC package 2320 and the circuit board 2302 are attached to opposing sides of the interposer 2304; in other embodiments, the IC package 2320 and the circuit board 2302 may be attached to the same side of the interposer 2304. In some embodiments, three or more components may be interconnected by way of the interposer 2304.

The interposer 2304 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2304 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, including but not limited to through-silicon vias (TSVs) 2306. The interposer 2304 may further include embedded devices 2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) protection devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2304. The package-on-interposer structure 2336 may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly 2300 may include an IC package 2324 coupled to the first face 2340 of the circuit board 2302 by coupling components 2322. The coupling components 2322 may take the form of any of the embodiments discussed above with reference to the coupling components 2316, and the IC package 2324 may take the form of any of the embodiments discussed above with reference to the IC package 2320.

The IC device assembly 2300 illustrated in FIG. 10 includes a package-on-package structure 2334 coupled to the second face 2342 of the circuit board 2302 by coupling components 2328. The package-on-package structure 2334 may include an IC package 2326 and an IC package 2332 coupled together by coupling components 2330 such that the IC package 2326 is disposed between the circuit board 2302 and the IC package 2332. The coupling components 2328 and 2330 may take the form of any of the embodiments of the coupling components 2316 discussed above, and the IC packages 2326 and 2332 may take the form of any of the embodiments of the IC package 2320 discussed above. The package-on-package structure 2334 may be configured in accordance with any of the package-on-package structures known in the art.

FIG. 11 is a block diagram of an example computing device 2400 that may include one or more components with one or more IC devices with backend memory and air gaps in upper metal layers in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the computing device 2400 may include a die (e.g., the die 2002 (FIG. 7B)) including one or more IC devices with backend memory and air gaps in upper metal layers in accordance with any of the embodiments disclosed herein. Any of the components of the computing device 2400 may include an IC device 2100 (FIG. 8 ) and/or an IC package 2200 (FIG. 9 ). Any of the components of the computing device 2400 may include an IC device assembly 2300 (FIG. 10 ).

A number of components are illustrated in FIG. 11 as included in the computing device 2400, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single SoC die.

Additionally, in various embodiments, the computing device 2400 may not include one or more of the components illustrated in FIG. 11 , but the computing device 2400 may include interface circuitry for coupling to the one or more components. For example, the computing device 2400 may not include a display device 2406, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2406 may be coupled. In another set of examples, the computing device 2400 may not include an audio input device 2418 or an audio output device 2408, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2418 or audio output device 2408 may be coupled.

The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2402 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which may itself include one or more memory devices such as volatile memory (e.g., DRAM), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 2404 may include memory that shares a die with the processing device 2402. This memory may be used as cache memory. The memory 2404 may include one or more IC devices with backend memory and air gaps in upper metal layers as described herein.

In some embodiments, the computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, the communication chip 2412 may be configured for managing wireless communications for the transfer of data to and from the computing device 2400. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

The communication chip 2412 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 602.11 family), IEEE 602.16 standards (e.g., IEEE 602.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 602.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 602.16 standards. The communication chip 2412 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2412 may operate in accordance with other wireless protocols in other embodiments. The computing device 2400 may include an antenna 2422 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

In some embodiments, the communication chip 2412 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2412 may include multiple communication chips. For instance, a first communication chip 2412 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2412 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2412 may be dedicated to wireless communications, and a second communication chip 2412 may be dedicated to wired communications.

The computing device 2400 may include battery/power circuitry 2414. The battery/power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2400 to an energy source separate from the computing device 2400 (e.g., AC line power).

The computing device 2400 may include a display device 2406 (or corresponding interface circuitry, as discussed above). The display device 2406 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

The computing device 2400 may include an audio output device 2408 (or corresponding interface circuitry, as discussed above). The audio output device 2408 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry, as discussed above). The audio input device 2418 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry, as discussed above). The GPS device 2416 may be in communication with a satellite-based system and may receive a location of the computing device 2400, as known in the art.

The computing device 2400 may include an other output device 2410 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The computing device 2400 may include an other input device 2420 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.

Select Examples

The following paragraphs provide various examples of the embodiments disclosed herein.

Example 1 provides an IC device that includes a frontend (e.g., FEOL) layer, including a plurality of frontend devices; and a backend layer, including a layer that includes a plurality of backend memory cells and a layer that includes a plurality of conductive interconnects coupled to one or more of the plurality of backend memory cells and the plurality of frontend devices, where at least some pairs of adjacent conductive interconnects of the plurality of conductive interconnects have an air gap between the adjacent conductive interconnects, and the layer that includes the plurality of backend memory cells is between the frontend layer and the layer that includes the plurality of conductive interconnects.

Example 2 provides the IC device according to example 1, where an average pitch (e.g., a center-to-center distance) of the plurality of conductive interconnects is at least about 200 nanometers, including all values and ranges therein, e.g., at least about 300 nanometers or at least about 350 nanometers.

Example 3 provides the IC device according to examples 1 or 2, where a width of the air gap at about half of a height of the air gap is at least about 70 nanometers, including all values and ranges therein, e.g., at least about 80 nanometers or at least about 100 nanometers.

Example 4 provides the IC device according to any one of the preceding examples, where a width of the air gap at a first distance from the frontend layer is greater than a width of the air gap at a second distance from the frontend layer, where the second distance is greater than the first distance. Thus, the air gap gets narrower and may be pinched at the top.

Example 5 provides the IC device according to any one of the preceding examples, where the air gap has an obelisk shape.

Example 6 provides the IC device according to any one of the preceding examples, further including a layer of a sealing material conformal to sidewall and top surfaces of the plurality of conductive interconnects and between bottoms of the plurality of conductive interconnects. In some further examples, sidewalls and a bottom of the air gap may also include the layer of the sealing material. In various examples, a thickness of the layer of the sealing material may be between about 2 and 10 nanometers, including all values and ranges therein, e.g., around about 4 nanometers.

Example 7 provides the IC device according to any one of the preceding examples, further including a layer of a barrier material over inner sidewalls of the plurality of conductive interconnects and at a bottom of at least some of the plurality of conductive interconnects.

Example 8 provides the IC device according to any one of the preceding examples, where a layer of a sealing material is at least partially at a first sidewall, a bottom, and a second sidewall of the air gap; an individual pair of the adjacent conductive interconnects with the air gap in between includes a first conductive interconnect and a second conductive interconnect; the sealing material at the first sidewall of the air gap is in contact with a conductive material of the first conductive interconnect; the sealing material at the second sidewall of the air gap is in contact with a conductive material of the second conductive interconnect; and the sealing material at the bottom of the air gap is in contact with an ILD material of the backend layer.

Example 9 provides the IC device according to example 8, where the ILD material is a first ILD material, a layer of a second ILD material is at least partially at the first sidewall, the bottom, and the second sidewall of the air gap, the sealing material at the first sidewall of the air gap is between the conductive material of the first conductive interconnect and the second ILD material at the second sidewall of the air gap, the sealing material at the second sidewall of the air gap is between the conductive material of the second conductive interconnect and the second ILD material at the second sidewall of the air gap, and the sealing material at the bottom of the air gap is between the first ILD material and the second ILD material at the bottom of the air gap.

Example 10 provides the IC device according to example 9, where a layer of an ES material is at least partially at the first sidewall, the bottom, and the second sidewall of the air gap, the ES material at the first sidewall of the air gap is between the sealing material at the first sidewall of the air gap and the second ILD material at the second sidewall of the air gap, the ES material at the second sidewall of the air gap is between the sealing material at the second sidewall of the air gap and the second ILD material at the second sidewall of the air gap, and the ES material at the bottom of the air gap is between the sealing material at the bottom of the air gap and the second ILD material at the bottom of the air gap.

Example 11 provides the IC device according to example 10, where the ES material is further over top surfaces of at least some of the plurality of conductive interconnects.

Example 12 provides the IC device according to any one of examples 8-11, where the conductive material of the first conductive interconnect is a first barrier material, and the first conductive interconnect further includes a first fill material, and the conductive material of the second conductive interconnect is a second barrier material, and the second conductive interconnect further includes a second fill material.

Example 13 provides the IC device according to any one of the preceding examples, where the plurality of backend memory cells include embedded DRAM (eDRAM) cells.

Example 14 provides the IC device according to any one of the preceding examples, where an individual one of the plurality of backend memory cells includes an access transistor and a capacitor.

Example 15 provides the IC device according to example 14, where the access transistor is a TFT.

Example 16 provides the IC device according to examples 14 or 15, where the capacitor is a cylindrical MIM capacitor.

Example 17 provides the IC device according to any one of the preceding examples, where the plurality of conductive interconnects is a plurality of conductive lines.

Example 18 provides an IC package that includes an IC device according to any one of the preceding examples; and a further IC component, coupled to the IC device. For example, the IC device may include a frontend layer with a plurality of frontend transistors, and a metallization stack over the frontend layer, the metallization stack including a backend memory layer with a plurality of memory cells with backend transistors, a layer with a plurality of conductive lines, where the backend memory layer is between the frontend layer and the layer with the plurality of conductive lines, and air gaps between adjacent ones of the plurality of conductive lines.

Example 19 provides the IC package according to example 18, where the layer with the plurality of conductive lines and with the air gaps between adjacent ones of the plurality of conductive lines is at or above a seventh layer (M7) of the metallization stack.

Example 20 provides the IC package according to examples 18 or 19, where no memory cells are included in the metallization stack further away from the frontend layer than the layer with the plurality of conductive lines and with the air gaps between adjacent ones of the plurality of conductive lines.

In some further examples of the IC package according to any one of examples 18-20, the further IC component includes one of a package substrate, an interposer, or a further IC die.

In some further examples of the IC package according to any one of examples 18-20, the IC device includes, or is a part of, at least one of a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communications device.

Example 21 provides an electronic device that includes a carrier substrate; and one or more of the IC device according to any one of the preceding examples and the IC package according to any one of the preceding examples, coupled to the carrier substrate.

Example 22 provides the electronic device according to example 21, where the carrier substrate is a motherboard.

Example 23 provides the electronic device according to example 21, where the carrier substrate is a PCB.

Example 24 provides the electronic device according to any one of examples 21-23, where the electronic device is a wearable electronic device (e.g., a smart watch) or handheld electronic device (e.g., a mobile phone).

Example 25 provides the electronic device according to any one of examples 21-24, where the electronic device further includes one or more communication chips and an antenna.

Example 26 provides the electronic device according to any one of examples 21-25, where the electronic device is an RF transceiver.

Example 27 provides the electronic device according to any one of examples 21-25, where the electronic device is one of a switch, a power amplifier, a low-noise amplifier, a filter, a filter bank, a duplexer, an upconverter, or a downconverter of an RF communications device, e.g., of an RF transceiver.

Example 28 provides the electronic device according to any one of examples 21-25, where the electronic device is a computing device.

Example 29 provides the electronic device according to any one of examples 21-28, where the electronic device is included in a base station of a wireless communication system.

Example 30 provides the electronic device according to any one of examples 21-28, where the electronic device is included in a user equipment device (i.e., a mobile device) of a wireless communication system.

Example 31 provides a method of fabricating an IC device. The method includes providing, over a semiconductor material, a frontend (e.g., FEOL) layer, comprising a plurality of frontend devices; providing, over the frontend layer, a layer that includes a plurality of backend memory cells; providing, over the layer that includes the plurality of backend memory cells, a layer of a first ILD material; forming a plurality of conductive lines in the layer of the first ILD material; recessing the first ILD material so that top surfaces and at least portions of sidewalls of the plurality of conductive lines are exposed; depositing a conformal layer of a sealing material over the top surfaces and the at least portions of sidewalls that have been exposed and over the first ILD material recessed between adjacent ones of the plurality of conductive lines; and, after depositing the conformal layer of the sealing material, depositing a second ILD material over the top surfaces that have been exposed so that air gaps remain between the adjacent ones of the plurality of conductive lines where the first ILD material has been recessed.

Example 32 provides the method according to example 31, where the second ILD material is present on at least portions of sidewalls and bottoms of the air gaps.

Example 33 provides the method according to examples 31 or 32, further including, after depositing the conformal layer of the sealing material and before depositing the second ILD material, depositing an ES material over the top surfaces that have been exposed so that air gaps remain between the adjacent ones of the plurality of conductive lines where the first ILD material has been recessed.

Example 34 provides the method according to example 33, where the ES material is present on at least portions of sidewalls and bottoms of the air gaps.

Example 35 provides the method according to any one of examples 31-34, where an average pitch (e.g., a center-to-center distance) of the plurality of conductive lines is at least about 200 nanometers, including all values and ranges therein, e.g., at least about 300 nanometers or at least about 350 nanometers.

Example 36 provides the method according to any one of examples 31-35, where an average width of the air gaps at about half of a height of the air gaps is at least about 70 nanometers, including all values and ranges therein, e.g., at least about 80 nanometers or at least about 100 nanometers.

Example 37 provides the method according to any one of examples 31-36, where the air gaps are in a metal layer of a metallization stack of the IC device that is a layer 7 (M7) or higher.

Example 38 provides the method according to any one of examples 31-37, where no backend memory cells are present in the IC device further away from the frontend layer than a layer with the air gaps.

Example 39 provides the method according to any one of examples 31-38, where the plurality of backend memory cells include thin-film transistors.

Example 40 provides the method according to any one of examples 31-39, further including processes for forming the IC device according to any one of the preceding examples (e.g., for forming the IC device according to any one of examples 1-17), and/or processes for forming the IC package according to any one of the preceding examples (e.g., for forming the IC package according to any one of examples 18-20), and/or processes for forming the electronic device according to any one of the preceding examples (e.g., for forming the electronic device according to any one of examples 21-30).

The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description. 

1. An integrated circuit (IC) device, comprising: a frontend layer, comprising a plurality of frontend devices; and a backend layer, comprising a layer that includes a plurality of backend memory cells and a layer that includes a plurality of conductive interconnects coupled to one or more of the plurality of backend memory cells and the plurality of frontend devices, wherein: at least some pairs of adjacent conductive interconnects of the plurality of conductive interconnects have an air gap between the adjacent conductive interconnects, and the layer that includes the plurality of backend memory cells is between the frontend layer and the layer that includes the plurality of conductive interconnects.
 2. The IC device according to claim 1, wherein an average pitch of the plurality of conductive interconnects is at least about 200 nanometers.
 3. The IC device according to claim 1, wherein a width of the air gap at about half of a height of the air gap is at least about 70 nanometers.
 4. The IC device according to claim 1, wherein a width of the air gap at a first distance from the frontend layer is greater than a width of the air gap at a second distance from the frontend layer, wherein the second distance is greater than the first distance.
 5. The IC device according to claim 1, wherein the air gap has an obelisk shape.
 6. The IC device according to claim 1, further including: a layer of a sealing material conformal to sidewall and top surfaces of the plurality of conductive interconnects and between bottoms of the plurality of conductive interconnects.
 7. The IC device according to claim 1, further including a layer of a barrier material over inner sidewalls of the plurality of conductive interconnects and at a bottom of at least some of the plurality of conductive interconnects.
 8. The IC device according to claim 1, wherein: a sealing material is at least partially at a first sidewall, a bottom, and a second sidewall of the air gap, an individual pair of the adjacent conductive interconnects with the air gap in between includes a first conductive interconnect and a second conductive interconnect, the sealing material at the first sidewall of the air gap is in contact with a conductive material of the first conductive interconnect, the sealing material at the second sidewall of the air gap is in contact with a conductive material of the second conductive interconnect, and the sealing material at the bottom of the air gap is in contact with an interlayer dielectric (ILD) material of the backend layer.
 9. The IC device according to claim 8, wherein: the ILD material is a first ILD material, a second ILD material is at least partially at the first sidewall, the bottom, and the second sidewall of the air gap, the sealing material at the first sidewall of the air gap is between the conductive material of the first conductive interconnect and the second ILD material at the second sidewall of the air gap, the sealing material at the second sidewall of the air gap is between the conductive material of the second conductive interconnect and the second ILD material at the second sidewall of the air gap, and the sealing material at the bottom of the air gap is between the first ILD material and the second ILD material at the bottom of the air gap.
 10. The IC device according to claim 9, wherein: an etch-stop (ES) material is at least partially at the first sidewall, the bottom, and the second sidewall of the air gap, the ES material at the first sidewall of the air gap is between the sealing material at the first sidewall of the air gap and the second ILD material at the second sidewall of the air gap, the ES material at the second sidewall of the air gap is between the sealing material at the second sidewall of the air gap and the second ILD material at the second sidewall of the air gap, and the ES material at the bottom of the air gap is between the sealing material at the bottom of the air gap and the second ILD material at the bottom of the air gap.
 11. The IC device according to claim 10, wherein: the ES material is further over top surfaces of at least some of the plurality of conductive interconnects.
 12. The IC device according to claim 8, wherein: the conductive material of the first conductive interconnect is a first barrier material, and the first conductive interconnect further includes a first fill material, and the conductive material of the second conductive interconnect is a second barrier material, and the second conductive interconnect further includes a second fill material.
 13. The IC device according to claim 1, wherein the plurality of backend memory cells include embedded dynamic random-access memory (eDRAM) cells.
 14. The IC device according to claim 1, wherein an individual one of the plurality of backend memory cells includes an access transistor and a capacitor.
 15. The IC device according to claim 1, wherein the plurality of conductive interconnects is a plurality of conductive lines.
 16. An integrated circuit (IC) package, comprising: an IC device; and a further IC component, coupled to the IC device, wherein the IC device includes: a frontend layer with a plurality of frontend transistors, and a metallization stack over the frontend layer, the metallization stack including: a backend memory layer with a plurality of memory cells with backend transistors, a layer with a plurality of conductive lines, where the backend memory layer is between the frontend layer and the layer with the plurality of conductive lines, and air gaps between adjacent ones of the plurality of conductive lines.
 17. The IC package according to claim 16, wherein the layer with the plurality of conductive lines and with the air gaps between adjacent ones of the plurality of conductive lines is at or above a seventh layer of the metallization stack.
 18. The IC package according to claim 16, wherein no memory cells are included in the metallization stack further away from the frontend layer than the layer with the plurality of conductive lines and with the air gaps between adjacent ones of the plurality of conductive lines.
 19. A method of fabricating an integrated circuit (IC) device, the method comprising: providing, over a semiconductor material, a frontend layer, comprising a plurality of frontend devices; providing, over the frontend layer, a layer that includes a plurality of backend memory cells; providing, over the layer that includes the plurality of backend memory cells, a layer of a first interlayer dielectric (ILD) material; forming a plurality of conductive lines in the layer of the first ILD material; recessing the first ILD material so that top surfaces and at least portions of sidewalls of the plurality of conductive lines are exposed; depositing a conformal layer of a sealing material over the top surfaces and the at least portions of sidewalls that have been exposed and over the first ILD material recessed between adjacent ones of the plurality of conductive lines; and after depositing the conformal layer of the sealing material, depositing a second ILD material over the top surfaces that have been exposed so that air gaps remain between the adjacent ones of the plurality of conductive lines.
 20. The method according to claim 19, further including: after depositing the conformal layer of the sealing material and before depositing the second ILD material, depositing an etch-stop material over the top surfaces that have been exposed so that air gaps remain between the adjacent ones of the plurality of conductive lines. 